1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to various methods of making a capacitor with a sealing liner and a semiconductor device including such a capacitor.
2. Description of the Related Art
In modern ultra-high density integrated circuits, device features have been steadily decreasing in size to enhance the performance of the semiconductor device and the overall functionality of the circuit. However, commensurate with the on-going shrinkage of feature sizes, certain size-related problems arise that may at least partially offset the advantages that may be obtained by simple size reduction alone. Generally speaking, decreasing the size of, for instance, circuit elements such as MOS transistors and the like, may lead to superior performance characteristics due to a decreased channel length of the transistor element, thereby resulting in higher drive current capabilities and enhanced switching speeds. Upon decreasing channel length, however, the pitch between adjacent transistors likewise decreases, thereby limiting the size of the conductive contact elements—e.g., those elements that provide electrical connection to the transistor, such as contact vias and the like—that may fit within the available real estate. Accordingly, the electrical resistance of conductive contact elements becomes a significant issue in the overall transistor design, since the cross-sectional area of these elements is similarly decreased. Moreover, the cross-sectional area of the contact vias, together with the characteristics of the materials they comprise, may have a significant influence on the effective electrical resistance and overall performance of these circuit elements.
Thus, improving the functionality and performance capability of various metallization systems has become important in designing modern semiconductor devices. One example of such improvements is the enhanced use of copper metallization systems in integrated circuit devices and the use of so-called “ultra-low-k” dielectric materials (“ULK” materials having a dielectric constant less than 2.8 in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior art metallization systems using tungsten for the conductive lines and vias. The use of ULK dielectric materials also tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk as compared to other dielectric materials with higher dielectric constants.
However, the use of such ULK materials is not without drawbacks. For example, such ULK materials tend to be more porous than dielectric materials having a higher k value.
While the increased porosity of the ULK materials, and thus the very low k value of such materials, is beneficial to many aspects of an integrated circuit device, e.g., reduced cross-talk, increased operating speed, such porosity can create problems when it comes to manufacturing certain types of devices. As one example, an illustrative eDRAM (embedded dynamic random access memory) array includes, among other things, a plurality of capacitors 110 (e.g., either single-sided or double-sided capacitors) that are electrically coupled to a plate contact. The capacitors are formed in a layer ULK dielectric material such as, for example, porous SiCOH (k32 2.4), that is formed above the surface of a semiconducting substrate. The capacitor typically has a metal-insulator-metal (MIM) configuration that includes a bottom electrode, a top electrode and a layer of insulating material positioned between the bottom electrode and the top electrode. Such a capacitor is typically formed by defining an opening in a layer of ULK material, conformably depositing a first metal layer (the bottom electrode), e.g., titanium nitride, in the opening, forming a layer of insulating material (e.g., a high-k material having a dielectric constant greater than 10) on the first metal layer and thereafter, filling the remaining portions of the opening in the ULK material with another metal, such as titanium.
In some cases, the ULK material may have openings that are approximately 2 nm in size. The first metal layer is typically formed by performing a chemical based process, such as an atomic layer deposition (ALD) process that involves the use of certain precursors. In the case where the first metal layer is titanium nitride, the deposition process involves the use of an organic metal nitride precursor that has a particle size of about 0.7 nm. During this formation of the first metal layer, some of the precursor material may infiltrate the ULK material at least to some degree. In turn, such infiltrating precursor material can lead several problems, such as the creation of undesirable regions of higher conductivity in the ULK material, the creation of conductive paths that may lead to short circuits, the undesirable increase (at least locally) in the k value of the ULK materials, etc. Such problems can lead to reduced device performance and, in some cases, to complete device failure.
The present disclosure relates to methods and devices for avoiding or at least reducing the effects of one or more of the problems identified above.